This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-125746, filed May 6, 1999; and No. 2000-130412, filed Apr. 28, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a MOS type semiconductor device, particularly, to a method of forming source/drain regions and a MOS type semiconductor device obtained by employing this forming method.
In the case of forming diffusion regions forming the source/drain regions in a semiconductor integrated circuit device having a MOS transistor, it is necessary to form shallow the diffusion regions in order to suppress the short channel effect of the transistor. A so-called xe2x80x9celevated source/drain structurexe2x80x9d, in which silicon is elevated in only the source/drain regions, is known to the art as an effective means for maintaining a low resistance of the diffusion regions.
The general method for achieving the elevated source/drain structure is to selectively grow silicon layers on the source/drain regions by using a selective growth method. For realizing a silicon growth on the silicon substrate while not growing a silicon on the insulating film in the selective silicon growth, it is absolutely necessary to apply a pretreatment of the selective growth to remove sufficiently the native oxide film formed on the silicon layer. As the result, a single crystalline silicon layer is formed on the source/drain regions. Several other methods have also been tried to date.
How to prepare a conventional MOS transistor having an elevated source/drain structure will now be described with reference to FIGS. 14 and 15. FIGS. 14 and 15 are cross sectional views showing a process of manufacturing a MOS transistor. A gate oxide film (SiO2) 102 is formed by, for example, thermal oxidation on the main surface of an n-type silicon semiconductor substrate 101, followed by forming a gate electrode 103 made of, for example, polycrystalline silicon and having a side wall insulating film 104 (FIG. 14A). Then, the gate oxide film 102 positioned outside an area in which the gate oxide film 102 is formed, is removed by etching. Further, the native oxide film formed on the exposed surface of the semiconductor substrate is removed by using an aqueous solution of hydrofluoric acid, followed by selectively performing growth of a silicon single crystalline film 105 in a thickness of about 50 nm on the exposed surface of the semiconductor substrate by using a CVD (Chemical Vapor Deposition) apparatus, (FIG. 14B). At this time, a polycrystalline silicon film 105xe2x80x2 is grown on the gate electrode 103. Silane gas, for example, is used for the growth of the silicon single crystalline film 105. Then, a p-type impurity such as boron (BF2) is introduced through the selectively grown silicon single crystalline film 105 by ion implantation under the condition with acceleration energy of 10 keV and at a dose of 5xc3x971015cmxe2x88x922 (FIG. 15A). Further, a heat treatment is applied by RTA (Rapid thermal annealing) at 800xc2x0 C. for 10 seconds for diffusing the implanted impurity so as to form p-type impurity diffusion regions forming a source region 107 and a drain region 108 (FIG. 15B).
As described above, in the elevated source/drain structure, the doping to the source/drain regions is performed by the ion implantation of the dopant after selective growth of a silicon layer in an attempt to form shallow diffusion layers. The thickness of the silicon single crystalline layer is increased by the selective growth so as to achieve a shallow diffusion layer, compared with the case where the selective growth is not carried out. However, since the grown film is single crystalline, the channeling in the ion implantation step is unavoidable. For avoiding the channeling problem, it is desirable to employ a selective growth of polycrystalline silicon. However, it is necessary to remove the native oxide film for the reason as described above, with the result that the grown film tends to become single crystalline. Such being the situation, it was difficult to form a polysilicon film by the selective growth. Incidentally, the selective growing method of polysilicon is described in, for example, Japanese Patent Application No. 3-149127 and xe2x80x9cF. Mieno et al Journal of Electrochemical Society vol. 134, p. 2862(1987)xe2x80x9d. In these prior arts, the deposited silicon film is allowed to contain a high concentration of carbon and oxygen so as to make the deposited silicon layer polycrystalline. As a result, it is unavoidable for the formed polysilicon layer to exhibit a high resistance, giving rise to a problem in using the polysilicon film as a conductive material.
The present invention has been achieved in view of above-mentioned circumstances, and has its object to provide a method of manufacturing a semiconductor device, which permits suppressing the channeling in the impurity doping step by an ion implantation method for forming the source/drain regions, which permits forming a shallow impurity diffusion region having a low resistance, and which also permits forming a fine MOS transistor advantageous in coping with the short-channel (short) effect.
In the present invention, a SiGe or SiC layer is selectively grown on the source/drain regions, followed by selectively growing a silicon layer. By setting the C or Ge content at a level higher than a predetermined concentration, a single crystal layer having a high dislocation density or a polysilicon layer is allowed to grow in the forming step of the silicon film. In the step of selective growth of a silicon layer, the silicon layer on the source/drain regions is not a single crystal. Even if the silicon layer is a single crystal, the silicon layer has a dislocation density. Therefore, the silicon film formed thereon is a single crystal having a high density of dislocation or a polysilicon. It follows that it is possible to prevent the difficulty caused by the channeling of ions generated in the impurity doping step by ion implantation for forming the source/drain regions. To be more specific, it is possible to prevent the impurity from being diffused to reach a deep region, making it possible to form a shallow impurity diffusion region having a low resistance, compared with the prior art in which a single crystal film prominently low in defects is grown selectively. It should also be noted that, since the diffusion coefficient within the deposited region is higher than that within the semiconductor substrate, it is possible to obtain an impurity diffusion region having a step-profile. As a result, it is possible to form a fine MOS transistor advantageous in terms of the short-channel effect.
A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate insulating film and a gate electrode on a main surface of a silicon semiconductor substrate; selectively depositing on only the exposed region of the main surface of the semiconductor substrate a conductive film containing germanium or a conductive film made of silicon carbide; depositing a silicon film on the conductive film of the region; and forming source/drain regions by implanting and diffusing an impurity into the main surface of the semiconductor substrate through the conductive film and the silicon film deposited on the conductive film with the gate electrode used as a mask. The silicon film deposited on the conductive film may be a polycrystalline film or a monocrystalline film having a dislocation density of at least 108cmxe2x88x922. The manufacturing method may further comprise the step of forming extension regions in predetermined regions for forming the source/drain regions, wherein the step is performed after formation of the gate electrode and before deposition of the conductive film containing germanium or conductive film made of silicon carbide. The manufacturing method may further comprise the step of lowering the resistance of the surface of the silicon film deposited on the conductive film. The step of lowering the resistance of the surface of the silicon film deposited on the conductive film may include a step of depositing a metal film on the surface of the deposited silicon film. A CoSi2 film, for example, may be formed on the silicon film surface to lower the resistance. The manufacturing method may further comprise the step of forming a side wall insulating film on the side surface of the gate electrode. The silicon carbide film may have a film thickness of 0.1 to 10 nm. The conductive film containing germanium may contain at least 20 atomic % of germanium. The conductive film containing germanium may contain at least 1xc3x971016cmxe2x88x922 of germanium in terms of areal density. The conductive film made of silicon carbide may contain at least 1xc3x971016cmxe2x88x922 of silicon carbide in terms of areal density.
Furthermore, a method of manufacturing a semiconductor device, according to the present invention comprises the steps of forming a gate insulating film and a gate electrode on a main surface of a silicon semiconductor substrate; selectively carbonizing only the exposed region of the main surface of the semiconductor substrate to selectively form a silicon carbide film on the exposed region, after formation of the gate electrode; depositing a silicon film on the silicon carbide film of the region; and forming source/drain regions by implanting and diffusing an impurity into the main surface of the semiconductor substrate through the silicon carbide film and the silicon film deposited on the silicon carbide film with the gate electrode used as a mask. The manufacturing method may further comprise the step of forming extension regions in predetermined regions for forming the source/drain regions, wherein the step is performed after formation of the silicon carbide film and before deposition of the silicon film on the silicon carbide film. The manufacturing method may further comprise the step of lowering the resistance of the surface of the deposited silicon film. The step of lowering the resistance of the surface of the deposited silicon film may include a step of depositing a metal film on the surface of the deposited silicon film. The manufacturing method may further comprise the step of forming a side wall insulating film on the side surface of the gate electrode. The silicon carbide film may have a film thickness of 0.1 to 10 nm.
Also, a semiconductor device according to the present invention comprises a silicon semiconductor substrate; a gate insulating film and a gate electrode formed on a main surface of the semiconductor substrate; a conductive film containing germanium or a conductive film made of silicon carbide, the conductive film being formed on a silicon-exposed region on the main surface of the semiconductor substrate; a silicon film formed on the conductive film on the region; and source/drain regions formed in the silicon semiconductor substrate region below the silicon film and the conductive film, wherein the silicon film is a polycrystalline film or a monocrystalline film having a dislocation density of at least 108cmxe2x88x922. The silicon film deposited on the conductive film may be a polycrystalline film or a monocrystalline film having a dislocation density of at least 108cmxe2x88x922. The conductive film containing germanium may contain at least 20 atomic % of germanium. The conductive film containing germanium may contain at least 1xc3x971016cmxe2x88x922 of germanium in terms of areal density. The silicon carbide film may have a film thickness of 0.1 to 10 nm.
The regions on which the conductive films are selectively deposited and the surface of the silicon substrate of which is partially exposed include the source/drain regions of a MOS transistor. In the source/drain regions of the MOS transistor, the distribution in a depth direction of a specified component such as germanium or carbon has a maximum value. The depth exhibiting the maximum value is in the vicinity of the gate insulator film. The dislocation density in a region shallower than the depth exhibiting the maximum value is higher than that in a region deeper than the depth exhibiting the maximum value. It is possible for the crystallinity in a region shallower than the depth exhibiting the maximum value to be polycrystalline. The diffusion coefficient of the dopant added to the source/drain regions is higher in a region shallower than the depth exhibiting the maximum value than in a region deeper than the depth exhibiting the maximum value.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.